1. Field of the Invention
The present invention relates to a semiconductor integrated circuit unit having a temperature protective circuit, and more particularly, to an improvement of the accuracy of the temperature protective function thereof.
2. Description of the Prior Art
Heretofore, many of semiconductor integrated-circuit units (hereinafter, called the IC (Integrated Circuit)) for driving a power transistor such as a power source device and a motor drive device are provided with a temperature protective circuit (so-called thermal shut-down circuit) as a means of preventing the IC from being broken due to an abnormal heat generation (especially, destruction of the power transistor generating the heat) (for example, refer to Japanese Laid-Open Patent No. 2004-253936 and Japanese Patent Publication No. H06-16540 by the applicant of the application).
Further, the conventional temperature protective circuit generally has been configured to produce a temperature protective signal by utilizing characteristics in that the Vf (forward dropping voltage) of a bipolar transistor or a diode fluctuates depending on the ambient temperature thereof
Further, the conventional temperature protective circuit generally has been of an automatic reset type having a hysteresis in threshold temperatures.
Other than above, as a conventional art in connection with the present invention, there have been disclosed and proposed a protective circuit in which a temperature protective circuit and an overcurrent protective circuit use a standard voltage generation section or an output section in common (refer to Japanese Laid-Open Patent No. H09-246876), and a semiconductor integrated-circuit for enhancing the drive current ability when a low temperature is detected (refer to Japanese Laid-Open Patent No. H07-161920).
Certainly, the conventional temperature protective circuit described above can detect and shut down an abnormal heat generation of the IC due to malfunction or overload, and thus prevent previously the breakage of the IC.
However, the conventional temperature protective circuit described above has a configuration such that the drive of a principal IC section is not stopped until the chip temperature reaches the threshold temperature, that is, an abnormal heat generation is detected, thus a preliminary temperature protective operation before the detection of abnormal heat generation being not particularly considered. For example, in the motor drive IC provided with the conventional temperature protective circuit, even if the indication of abnormal temperature rise is found, a torque control not different from regular operation is continuously performed unless the chip temperature reaches the threshold temperature. Hence, the conventional temperature protective circuit has a problem in that the circuit, even though finally can shut down the abnormal heat generation of the IC, cannot prevent the generation, thereby making the chip temperature easily increased.
Further, an IC provided with the conventional temperature protective circuit has a problem in that the output thereof is sharply turned off due to the shut-down operation at the abnormal heat generation, whereby various discrepant conditions (noise or serge generation) are apt to be introduced. For example, in a case where a subject of the IC to be driven is an L load having inductance components (such as motor coil), a counter-electromotive voltage developed in the L load concerned is jumped at the shut-down of the IC to exceed the withstand voltage thereof, whereby the IC can be broken.
Further, the conventional temperature protective circuit is often provided near a subject of overheat monitoring in order to improve the sensibility of the detection of abnormal heat generation. On the contrary, as a compensation, because the logic states (high level/low level) of the temperature protective signal are highly frequently repeated even though the threshold temperature is given the above-mentioned hysteresis, the automatic restart operation after shut-down can be in a state (logic oscillating state) in which the operation cannot be released from that state.